Integrated circuit manufacturers now deliver circuits containing tens of millions of gates. The ever-increasing complexity and speed of analog, digital and mixed-signal integrated circuits require appropriate and thorough test activities during development and production. Typically, a set of tests are performed sequentially on each device under test (DUT), and a test program measures target test specification values from the test responses obtained.
The test process is complicated, lengthy, and costly. One reason is that integrated circuits (ICs) are typically packaged before they are used with other components as part of a larger electronic system, and tests are performed on the IC at both the die stage and the packaged stage. Tests that focus on internal portions of the IC package are commonly referred to as “first-level” tests, while tests that focus on the reliability or function of the connection between the IC package and the printed wiring board are commonly referred to as “second-level” tests.
First-level tests may involve calibration test, continuity test, and leakage tests, for example. In addition, IC's are being designed as system-on-chip (SoC) devices having embedded blocks and structures, all of which require test and debug. Whenever memories are integrated into an IC, appropriate tests have to be conducted to make sure that the IC is not shipped with faulty memories. Thus, ICs are manufactured with built-in self test structures for testing embedded cores that provide test control at the chip level.
In addition, device specific tests are also run. For example, a multi-gigahertz radiofrequency (RF) circuit may undergo receive (RX) and transmit (TX) test for testing receive and transmit components, respectively, of the circuit.
Second-level tests generally involve variations in electronic signal bias, ambient temperature, ambient humidity, etc. Second-level tests generally subject the IC package to thermal cycling conditions while electronic signals are supplied to the IC package. The electronic signals are monitored for failure conditions, such as an unacceptable increase in electronic resistance at any given temperature (e.g. −25° C. to +85° C.), which may occur due to thermal expansion and/or contraction of any portion of the IC package.
For example, one well-known type of second-level test is an electronic bias test commonly known as a highly accelerated stress test (HAST). To perform a HAST, the packages must be placed into a separate device, called a stress socket, that makes an external electronic connection with the package. The stress sockets containing the packages are then attached to a board, and the board is then placed into a HAST chamber for electronic testing.
Depending on the type of device, before or after HAST testing, devices may be placed into another type of test apparatus for automated electronic testing Automated test equipment (ATE) comprises various instruments or cards used for testing memory, digital, mixed signal and system-on-chip (SOC) components, both at the wafer and packaged stages.
As can be seen, the sheer number of tests that may be performed on an electronic device may number in the hundreds. For example, for radiofrequency (RF) and multi-gigahertz devices, it is not uncommon for the devices to undergo 600 tests. Some of these tests are redundant, waste test time, and fail to improve quality. As a result, test costs continue to rise due to the cost of external test instrumentation as well as the time required to complete all of the tests.
Accordingly, it would be desirable to reduce the overall test time required to test electronic devices, such as ICs and IC/packages.